Regular Papers
Full-length technical papers presenting original research in EDA and VLSI design automation.
Systems/CORE B
ASP-DAC 2027
Asia and South Pacific Design Automation Conference
ASP-DAC is the largest conference in Asia and the South Pacific focused on Electronic Design Automation (EDA) for VLSI and systems, offering a platform for presenting cutting-edge research in design automation, LSI design, and emerging technologies. The conference features technical papers, tutorials, special sessions, designers' forums, and the University LSI Design Contest, with a hybrid format emphasizing in-person participation.
Key deadlines
Verified September 9, 2026Abstract registration
July 3, 2026
AoE
Full paper
July 10, 2026
AoE
Conference timeline
Submission and decisions
Abstract registrationKey deadline
July 3, 2026 · AoE
Full paperKey deadline
July 10, 2026 · AoE
Paper fit
Contribution paths
A strong submission should clearly identify its contribution and evaluate it appropriately.
University LSI Design Contest Papers
Papers submitted by university teams participating in the University LSI Design Contest.
Invited Papers
Papers presented by invited speakers, including keynote and tutorial presenters.
Designers' Forum Papers
Presentations by designers showcasing latest real-world LSI designs and implementations.
Short Papers
Concise submissions presenting early-stage research or focused technical contributions.
Work-in-Progress (WIP) Papers
Papers presenting ongoing research, typically submitted as posters for informal discussion.
Research areas in scope
01
System-Level Modeling and Design Methodologies
System-Level Modeling and Design MethodologiesNext-Generation Embedded Architectures and ToolsSystem Level Modelling & Optimization
02
AI and Machine Learning in EDA
AI and Logic SynthesisAI/ML for Circuit Design and PredictionAI-Driven Innovative Design MethodsLeveraging Large Language Models in Hardware DesignMachine Learning Based Physical Simulation and Physics-Aware OptimizationML for IC Design and ManufacturingAdvanced Modeling, Simulation, and Verification
03
Computing-In-Memory and Emerging Architectures
Application-Specific Computing-In-MemoryFrameworks and Modeling for Computing-In-MemoryHybrid/Co-Designed Near/In Memory ComputingEmerging Trends in Reconfigurable and Compute-in-MemoryAdaptive and Flexible Memory ArchitectureNeuromorphic and Emerging Computing Techniques
04
EDA Tools and Design Automation
Automation of Standard Cell Layout Generation and Design-Technology Co-optimizationAHS: An EDA toolbox for Agile Chip Front-end DesignShaping the Future of Analog EDATiming Analysis and OptimizationFloorplan and PlacementReliability in Physical DesignPackage and PCBVerification and Testing in Machine Learning Era
05
Hardware Security and Trust
Side Channel Attacks and Trusted Execution EnvironmentLogic Locking and Hardware WatermarkingHomomorphic Encryption and Cloud SecurityHardware Authenticity towards a Trustworthy Society
06
On-Device AI and Edge Computing
Tools and Techniques for On-Device AI DeploymentEfficient Deployment of Large Language Models on Resource Constrained Edge Computing PlatformsLLM Acceleration and Specialization for Circuit Design and Edge ApplicationsInnovative Techniques in AI Model Optimization and Training
07
Photonic and Quantum Computing
Silicon PhotonicsThe Science of Light: the New Advancement of Photonic ComputingLet's Quantumize: Welcome to the World of QuantumQuantum Computing
08
Approximate and Stochastic Computing
Approximate and Stochastic ComputingHybrid Temporal Computing for Lower Power Hardware Accelerators
09
Designers' Forum and Special Sessions
Designers' ForumSpecial Sessions on Advanced Sensor Technologies and Sensor FusionSpecial Sessions on Rapidus' Initiatives to Half Semiconductor Development TimeSpecial Sessions on Innovations and Challenges on Cryo-CMOS Devices, Circuits and Design PlatformsSpecial Sessions on Beyond Digital: Advancing Design Automation for Physical Computing SystemsSpecial Sessions on Advances in 3D-IC and Ultra-Large-Scale IntegrationSpecial Sessions on CEDA/CASS/SSCS Joint Session on Silicon Photonics
Policies worth checking twice
- All presenters must attend their session either in-person or online; failure to present results in removal from proceedings and digital libraries.
- Pre-recorded video presentations are highly recommended for remote presenters and required if live attendance is not possible.
- No exemptions from the no-show policy will be granted without a pre-recorded video.
- Final manuscript submission is a hard deadline with no extensions.
- Camera-ready submissions must follow the official 'Submission GUIDE for Camera-Ready Manuscript'.
- Source files and PDF files must both be submitted for all paper types.
- Dual submission to other conferences or journals is not permitted.
- Author lists cannot be changed after the paper acceptance notification.
Official sources
Compiled from the official call for papers. The organizers’ pages remain authoritative.
Last verified September 9, 2026