Regular Papers
Original, unpublished papers up to 6 pages in IEEE 2-column format, covering all technical topics of ATS 2026. Accepted papers are submitted to IEEE Xplore and require at least one author registration and presentation.
Systems/CORE Unranked
ATS 2026
IEEE Asian Test Symposium
The IEEE 35th Asian Test Symposium (ATS 2026) is a premier international forum for academic researchers and industry professionals to exchange groundbreaking ideas and present the latest research in electronics testing. Held in Kaohsiung, Taiwan, from December 1–3, 2026, it covers a broad spectrum of test technologies for systems, modules, and devices, including emerging areas like AI, quantum computing, and 3D ICs.
Key deadlines
Verified September 9, 2026Full paper
June 6, 2026
AoE
Conference timeline
Submission and decisions
Full paperKey deadline
June 6, 2026 · AoE
Paper fit
Contribution paths
A strong submission should clearly identify its contribution and evaluate it appropriately.
Late-Breaking Results (LBR)
Extended abstracts up to 3 pages in IEEE 2-column format, showcasing emerging research, breakthroughs, or impactful project outcomes. Must present original and innovative work, peer-reviewed, and included in proceedings.
Special Session Proposals
Proposals for focused sessions on emerging topics, including invited talks, panels, or tutorials. Accepted proposals lead to either one 10-page consolidated paper or three 4-page individual papers, all subject to IEEE formatting and review.
Innovative Practices Session Proposals
Proposals highlighting industrial challenges and practical solutions in test, reliability, and dependable systems. Accepted proposals result in a one-page session abstract describing scope and contributions.
Research areas in scope
01
Technical Topics
AI test and Test for AIAnalog/Mixed-Signal TestATE DesignAutomatic Test Pattern Generation (ATPG)Autonomous TestingBoard-Level Testing and DiagnosisBoundary Scan TestBuilt-In Self-Test (BIST)CPU/GPU TestConnectivity TestingDefect-Based TestDelay and Performance TestDependability and Functional SafetyDesign Verification, Validation, and DebugDesign for Testability (DFT)Diagnosis and Silicon DebugFault Diagnosis and Failure AnalysisFault Modeling and SimulationFault ToleranceHardware Oriented Security and TrustHigh-Speed I/O TestHeterogeneous TestingLow-Power IC TestMachine Learning in TestMemory Test, Diagnosis, and RepairMulti-/Many-core Processor TestOnline TestOn-Chip MeasurementPower/Thermal/Reliability Issues in TestReconfigurable System TestReliability and Testing for Emerging/Approximate/Quantum ComputingRF TestSafety and Test for Automotive ICsSelf-RepairSiP, Chiplet, 2.5D and 3D IC TestSoftware Test and ReliabilityStandards in TestSystem-on-Chip TestTest CompressionTest EconomicsTest QualityTest SynthesisTest for Biomedical Circuits and SystemsTest for MEMS and Microfluidic SystemsTest for Nanoscale Devices and Emerging TechnologiesTest for Reversible and Quantum CircuitsTest for Sensors and IoTYield Analysis, Learning, and Enhancement
Policies worth checking twice
- Submissions must be original and unpublished.
- Regular papers must not exceed 6 pages in IEEE 2-column format (including abstract, figures, tables, and bibliography).
- Late-Breaking Results (LBR) submissions must not exceed 3 pages in IEEE 2-column format.
- All submissions must be in PDF format only.
- Submissions must be made via the official EasyChair system; email submissions are not accepted.
- At least one author of each accepted paper must register and attend the conference at full rate.
- Authors of accepted papers must submit camera-ready manuscripts by the deadline to be included in proceedings.
- Accepted papers are submitted to IEEE Xplore subject to meeting its scope and quality requirements.
Official sources
Compiled from the official call for papers. The organizers’ pages remain authoritative.
Last verified September 9, 2026