Full papers
Manuscripts up to 12 pages in single-column Springer LNCS format; no short paper track exists.
AI/CORE Unranked
DASIP2027 2027
DASIP 2027 Workshop
DASIP 2027 is a workshop on Design and Architectures for Signal and Image Processing, held in conjunction with HiPEAC 2027 in Glasgow, Scotland. It serves as an international forum for innovations in signal, image, and video processing, and machine learning on custom embedded, edge, and cloud computing architectures, with accepted papers published in Springer LNCS.
Paper fit
Contribution paths
A strong submission should clearly identify its contribution and evaluate it appropriately.
Research areas in scope
01
Architectures and Systems
Custom embedded, edge and cloud architectures and systemsMachine learning and deep learning architectures for inference and trainingSystems for autonomous vehicles: cars, drones, ships and space applicationsImage processing and compression architecturesSmart cameras, security systems, behaviour recognitionEdge and cloud processing: special routing, configurable coprocessors and low energy considerationsReal-time cryptography, secure computing, financial and personal data processingComputer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computingBiological data collection and analysis, bioinformaticsPersonal digital assistants, natural language processing, wearable computing and implantable devicesGlobal navigation satellite and inertial navigation systems
02
Design Methods and Tools
Design verification and fault toleranceEmbedded system security and security validationSystem-level design and hardware/software co-designHigh-level synthesis, logic synthesis, communication synthesisEmbedded real-time systems and real-time operating systemsRapid system prototyping, performance analysis and estimationFormal models, transformations, algorithm transformations and metrics
03
Development Platforms, Architectures and Technologies
Embedded platforms for multimedia and telecommunicationMany-core and multi-processor systems, SoCs, and NoCsReconfigurable ASIPs, FPGAs, and dynamically reconfigurable systemsMemory system and cache managementAsynchronous (self-timed) circuits and analog and mixed-signal circuits
Policies worth checking twice
- Submissions must describe original unpublished work and must not be under consideration for publication elsewhere.
- Submissions must be fully anonymous; self-references must be made in the third person.
- Each submission receives at least three independent double-blind reviews.
- All accepted papers must be presented by one of the authors to be included in the proceedings.
- A HiPEAC registration is required for each accepted paper, and at least one author must pay the full registration fee.
- Two-cycle submission process: papers rejected in the preliminary cycle may be resubmitted in the main cycle; acceptance in the preliminary cycle guarantees automatic acceptance in the main cycle.
Official sources
Compiled from the official call for papers. The organizers’ pages remain authoritative.
Last verified September 9, 2026