Full Paper
Papers up to 8 pages in length, formatted according to IEEE conference guidelines, submitted via EasyChair. Papers are double-blind reviewed and may be accepted as full papers or shortened to 4 pages.
Systems/CORE C
ICCD 2026
International Conference on Computer Design
The 44th IEEE International Conference on Computer Design (ICCD 2026) is a multidisciplinary forum for researchers and developers to present and discuss practical and theoretical work in computer systems and their components. The conference covers a broad spectrum of topics including computer architecture, verification and test, design tools, circuit design, and emerging technologies, with a focus on future systems and innovations.
Key deadlines
Verified September 9, 2026Abstract registration
May 30, 2026
AoE
Full paper
June 6, 2026
AoE
Conference timeline
Submission and decisions
Abstract registrationKey deadline
May 30, 2026 · AoE
Full paperKey deadline
June 6, 2026 · AoE
Paper fit
Contribution paths
A strong submission should clearly identify its contribution and evaluate it appropriately.
Short Paper
Papers of 4 pages, but not accepted during initial submission; may be offered as a reduced-length version of a full paper upon acceptance.
Special Session Proposal
90-minute sessions consisting of individual presentations or panel discussions on hot topics beyond traditional ICCD disciplines, submitted via EasyChair.
Tutorial Proposal
90-minute interactive sessions including technical presentations, demonstrations, or hands-on activities, submitted as a single PDF via EasyChair with details on content, organizers, and format.
Research areas in scope
01
Computing Systems
System architectureSoftware-hardware co-designSystem support for multi/many cores, co-processors/acceleratorsSystem support for speed, security, reliability, and energy efficiency and proportionalityVirtual memorySystem support for emerging technologiesStorage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale system, and serverless computing
02
Software Architectures, Compilers, and Tool Chains
Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systemsMiddleware for computing systems, including resource-awareness, reconfiguration, energy/power management, task schedulingCompiler support for enhanced debugging, profiling, and traceabilityProcessor modeling, optimization and simulation
03
Hardware Architectures
Design for high-performance, low-power, secure, and reliable processor microarchitecturesHardware acceleration for computing-intensive/data-intensive applications, such as machine learning, autonomous driving, robotics, quantum, neuromorphic, bio-inspired, etc.In-memory/near-memory computing architecturesHardware design with emerging technologies, including emerging memory, photonics, etc.
04
Test, Verification, and Security
Design error debug and diagnosisFault modelingFault simulation and ATPGAnalog/RF testingStatistical test methodsLarge volume yield analysis and learningFault toleranceDFT and BISTFunctional, transaction-level, RTL, and gate-level modeling and verification of hardware designsEquivalence checking, property checking, and theorem provingConstrained-random test generationHigh-level design and SoC validationHardware security primitives and methodologiesSide-channel analysis, attacks and mitigations for processors and acceleratorsInteraction between test, security and trust
05
Electronic Design Automation
System-level design and synthesisHigh-level, logic, and physical synthesisAnalysis and optimization of timing, power, variability/yield, temperature, and noisePhysical design, including partitioning, floor-planning, placement, routing, and clock tree synthesisTools for multiple-clock domains, asynchronous, and mixed-timing methodologiesCAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processorsCAD for manufacturing, test, verification, and securityTools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum)Interaction of Electronic Design Automation (EDA) and AI/ML
06
Logic and Circuit Design
Circuit design techniques for digital, memory, analog, and mixed-signal systemsHigh-performance and low-power circuit techniquesRobust circuit design under process variability, noise, radiation, and reliability constraintsEmerging and maturing device and circuit technologies, including MEMS, nano-spintronics, flexible electronics, in-memory computing, and quantum devicesAsynchronous circuit designSignal-processing, datapath, and control circuits, including quantum circuit optimization, qubit control and readout electronics, and circuit-level error mitigation techniques
Policies worth checking twice
- Submissions are double-blind: all author-identifying information must be removed.
- Papers must be formatted using IEEE conference guidelines with Letter page size and 10-pt font.
- Initial submissions are limited to 8 pages, including figures, references, and appendix.
- Each accepted paper must be accompanied by a unique full registration.
- Each accepted paper must be presented in person by one of the authors to be included in the proceedings.
- The list of authors, paper title, and abstract must be registered by the abstract submission deadline.
- The full paper must be submitted by the paper submission deadline.
- Short papers are not accepted during initial submission but may be offered as reduced-length versions upon acceptance.
Official sources
Compiled from the official call for papers. The organizers’ pages remain authoritative.
Official conference siteCall for PapersCall for TutorialsProgram CommitteeSubmission GuidelinesCFP_ICCD2026.pdf
Last verified September 9, 2026